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Electrical Characteristics
2.5
DC Electrical Characteristics
This section describes the DC electrical characteristics for the MSC8144.
2.5.1
DDR SDRAM DC Electrical Characteristics
This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8144.
Note:
DDR SDRAM uses V DDDDR (typ) = 2.5 V and DDR2 SDRAM uses V DDDDR (typ) = 1.8 V.
2.5.1.1
DDR2 (1.8 V) SDRAM DC Electrical Characteristics
Table 6 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MSC8144 when
V DDDDR (typ) = 1.8 V.
Table 6. DDR2 SDRAM DC Electrical Characteristics for V DDDDR (typ) = 1.8 V
I/O reference voltage
Parameter/Condition
I/O supply voltage 1
2
Symbol
V DDDDR
MV REF
Min
1.7
0.49 × V DDDDR
Max
1.9
0.51 × V DDDDR
Unit
V
V
I/O termination
voltage 3
V TT
MV REF – 0.04
MV REF + 0.04
V
Input high voltage
Input low voltage
V IH
V IL
MV REF + 0.125
–0.3
V DDDDR + 0.3
M V REF – 0.125
V
V
Output leakage
current 4
I OZ
–50
50
μ A
Output high current (V OUT = 1.420 V)
Output low current (V OUT = 0.280 V)
I OH
I OL
–13.4
13.4
—
—
mA
mA
Notes:
1.
2.
3.
4.
V DDDDR is expected to be within 50 mV of the DRAM V DD at all times.
MV REF is expected to be equal to 0.5 × V DDDDR , and to track V DDDDR DC variations as measured at the receiver.
Peak-to-peak noise on MV REF may not exceed ± 2% of the DC value.
V TT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MV REF . This rail should track variations in the DC level of V DDDDR .
Output leakage is measured with all outputs are disabled, 0 V ≤ V OUT ≤ V DDDDR .
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
29
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